Lead storage cells, nickel-cadmium storage cells, lithium-ion secondary cells, and the like have been developed and practically used as secondary cells capable of charging and storing electricity. Recently, all-solid-state secondary cells capable of being formed with thin films have been drawing attention and have been applied to small-sized devices with features of safety and space-saving for being mounted.
Patent Document 1 discloses a semiconductor device into which a solid-state thin film secondary cell is internally arranged in a monolithic manner by forming the solid-state thin film secondary cell on a substrate, and thereby, a semiconductor device in which an electronic element and the solid-state secondary cell are arranged as circuits in a monolithic manner. The solid-state thin film secondary cell is an all-solid-state lithium-ion secondary cell. The solid-state thin film secondary cell is internally arranged in a monolithic manner by forming the solid-state thin film secondary cell, on the substrate, as having a porous film formed through surface modification of a semiconductor element substrate as a negative-electrode active material.
As illustrated in FIG. 20, in an IC/LSI chip 116 of a semiconductor element substrate on which a monolithic secondary cell is mounted, solid-state thin film secondary cells formed in a monolithic manner are connected to IC/LSI portions respectively via internal wirings 112-1, 112-2. A monolithic solid-state thin film secondary cell group 110-1 that supplies power to a memory circuit unit 114 and a monolithic secondary cell group 110-2 that supplies power mainly to a logic circuit unit 113 are integrated on the substrate of the IC/LSI chip 116 together with a circuit group. Both of the above can be electrically connected respectively by a plurality of internal wirings. Although external wirings may be adopted, advantages of a monolithic type are considered to be drastically lost in such a case.
Patent Document 2 discloses a cell-mounted type integrated circuit device in which a semiconductor chip is mounted on a solid-state cell. The solid-state cell includes a charging element that includes a positive electrode, a negative electrode, and a solid electrolyte, and a protection film arranged outside the charging element. Here, the protection film has a multi-layer structure and at least one layer thereof has a positive electrical potential. It can be packaged with the protection film while preventing ions for charging-discharging from being diffused to the integrated circuit and preventing characteristic deterioration and false operation of the semiconductor device. Accordingly, it is possible to provide a cell-mounted type integrated circuit device having reduced mounting area.
In a chip illustrated in FIG. 21, silver paste is coated on a lead frame 120 prepared for cell-mounting and a solid-state cell 122 is heated at 200° C. and arranged thereon. Liquid epoxy resin is coated thereon and a semiconductor chip 124 is arranged. Then, wiring is performed with insulation-coated gold wires 128 having a diameter of 100 μm by soldering the semiconductor chip 124 and the lead frame 120, and the solid-state cell 122 and the lead frame 120. Sealing is performed with epoxy resin 126.
Patent Document 3 discloses a structure of an element of a thin film cell integration type in which a thin film cell and an element can be electrically connected without using connecting means such as a wire while the thin film cell is formed as being directly layered on a chip or the element.
It is structured to include the element, an insulating layer being an electrically non-conductive member that covers the element, a pair of element terminals vertically arranged on the element or a side face thereof, a pair of vertical conductive members having conductivity as being vertically arranged on the element terminals respectively from an upper end thereof to a position of the upper most surface of the insulating layer, and a thin film cell that includes a negative electrode thin film and a positive electrode thin film formed on the pair of vertical conductive members. Further, it is disclosed that a pair of electrode conductive members may be arranged as well that are electrically connected to the positive electrode and the negative electrode of the thin film cell as being arranged on the pair of vertical conductive members and as being horizontally distanced on the insulating layer.
Patent Document 4 discloses a structure that an all-solid-state cell is layered on a RAM chip. A passivation film is formed on a surface of the RAM, and a positive or negative electrode material film of the cell, a solid electrolyte film, and a negative or positive electrode material film are sequentially formed thereon. Regarding connection of the cell and the RAM chip, a power terminal and a ground terminal of a circuit integrated in a semiconductor are connected to the positive electrode and the negative electrode of the cell via a power collector.